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2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)
With aggressive CMOS technology scaling, Negative Bias Temperature Instability (NBTI) has emerged as one of the major system lifetime reliability threats, which gradually increases P-MOS transistor threshold voltage and hence results in increased circuit delay. NBTI-induced performance degradation depends heavily on time-varying parameters such as temperature, duty cycle and supply voltage. Previous analytical models for NBTI effects, however, cannot cover all these parameters, causing overlydoi:10.1109/dac.2014.6881496 fatcat:vxmiya7v7ja47jf32diizjgvwa