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Clock skew scheduling for soft-error-tolerant sequential circuits
2010
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Soft errors have been a critical reliability concern in nanoscale integrated circuits, especially in sequential circuits where a latched error can be propagated for multiple clock cycles and affect more than one output, more than once. This paper presents an analytical methodology for enhancing the soft error tolerance of sequential circuits. By using clock skew scheduling, we propose to minimize the probability of unwanted transient pulses being latched and also prevent latched errors from
doi:10.1109/date.2010.5456956
dblp:conf/date/WuM10
fatcat:qoqvn3qzzrao7gupflaayyrdsm