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Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

C. Yildirim, J.T. Butler, C. Yang
[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic  

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We analyze simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design. Of spec@c interest is the use of parallel processors. We consider the use of loosely-coupled, coarsegrainedparallel systems, and study the relationship between the quality of the solution and computation time, on the one hand, and simulated annealing parameters, start temperature, cooling rate, etc., on the other. We also investigate simulated annealing where there is a mixture of move types.
more » ... mixed move approach provides improvement in both the number of product terms and computation time.
doi:10.1109/ismvl.1993.289587 dblp:conf/ismvl/YildirimBY93 fatcat:wkpa52zxsfbungmgu7buuhphv4
Citation

C. Yildirim, J.T. Butler, C. Yang. "Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing." [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic 17-23