Scan Test Bandwidth Management for System-on-Chip Using FPGA

M Rajesh, P Scholar, A Mr, M Chakri Sreedhar, Tech
With the increase in chip size and complexity, the direct or bus interconnects in conventional SoC testcontrol models are rather restricted. In this paper, we propose a new distributed multihop wireless testcontrol network based on the recent development in-radio-on-chip‖ technology. The proposed architecture consists of three basic components, the test scheduler, the resource configurators, and the RF nodeswhich support the communication between the test scheduler and clusters of cores. Under
more » ... rs of cores. Under the multileveltree structure, the resources (including not only the circuit blocks to perform testing, but also the on-chipradio-frequency nodes for intra-chip communication) are properly distributed and system optimizationis performed in terms of both test application time and test control cost.