A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

Paul Beckett
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI
more » ... G-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly. Paul Beckett (M'06) was born in Melbourne, Australia, in 1953. He received the B.Eng. (Comm.), M.Eng., and Ph.D. degrees from the Royal Melbourne Institute of Technology (now RMIT University), Melbourne, in 1975Melbourne, in , 1984Melbourne, in , and 2007 He is currently a Senior Lecturer with the School of Electrical and Computer Engineering, RMIT University, where he teaches undergraduate and postgraduate courses in embedded computer architecture, digital logic, and VLSI design. His research interests include the design and simulation of nanoscale devices and the mixed-signal modeling of reconfigurable circuits and architectures. Authorized licensed use limited to: RMIT University. Downloaded on August 5, 2009 at 21:15 from IEEE Xplore. Restrictions apply.
doi:10.1109/tvlsi.2007.912024 fatcat:6guwuhgv2zao7fxbkewfqyps7u