A Versatile Variable Rate LDPC Codec Architecture

Colm P. Fewer, Mark F. Flanagan, Anthony D. Fagan
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules. Thus, rate compatibility is facilitated without the performance degradation inherent in a puncture-based system. This versatility also allows the LDPC system to be used in a variety of applications since the encoder and decoder can be used with codes that span a wide range of lengths and rates.
doi:10.1109/tcsi.2007.904641 fatcat:hg6rumlmynaeddeqvhef4cskam