14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers  
A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital library and place-and-routed automatically without any manual routing. The proposed PLL has been fabricated in a 28 nm fully depleted silicon on insulator (FDSOI) technology. The measurement results show that this synthesized injection-locked PLL consumes 1.4 mW
more » ... rom 1 V supply while achieving a figure of merit (FoM) of −235.0 dB with 1.5 ps RMS jitter at 1.6 GHz. This chip occupies only 64 µm × 64 µm layout area with the advanced 28 nm FDSOI process. To the best knowledge of the authors, the PLL presented in this paper achieves the smallest area to date.
doi:10.1109/isscc.2015.7063021 dblp:conf/isscc/DengYNNSOM15 fatcat:cxy4kmjrpbe2rhovo4nuswn7ba