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E 9 Power consumption and signal delay are crucial to the design of highperformance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based on device equations, and encapsulate logic gate behaviordoi:10.1109/tcad.1986.1270236 fatcat:7afhljyowbf6jarqvmq3vk6idq