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Carbon Nanotubes (CNTs) are grown using chemical synthesis, and the exact positioning and chirality of CNTs are very difficult to control. As a result, "small-width" Carbon Nanotube Field-Effect Transistors (CNFETs) can have a high probability of containing no semiconducting CNTs, resulting in CNFET failures. Upsizing these vulnerable smallwidth CNFETs is an expensive design choice since it can result in substantial area/power penalties. This paper introduces a processing/design co-optimizationdoi:10.1145/1837274.1837497 dblp:conf/dac/ZhangBPLWMM10 fatcat:hbcwbov4uzdgvmioik4fggybuu