Measurement and Modeling of Coupling Effects of CMOS On-Chip Co-Planar Inductors

J Kolding, T Mikkelsen, J Larsen, T Mikkelsen, T Kolding, Larsen
1998 Microwave Journal   unpublished
The work documented in this dissertation deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. The work has been divided into three parts: Part I of the dissertation is concerning CMOS as an RF technology, Part II deals with receiver architectures on a system level, and Part III considers RF circuit and device implementations in CMOS. Through comparison a historic background to the use of CMOS in cellular
more » ... plications is provided. The tremendous developments in CMOS technology are considered and the analog short-comings are evaluated. The lack of high quality passive devices, inductors in particular, is found to be one of the major obstacles in achieving a fully integrated RF design based on CMOS. Part II starts with an overview of different receiver architectures and a discussion of some fundamental problems in relation to CMOS integration. Based on the standards provided for Universal Mobile Telephone System (UMTS) requirements are derived for a UTRA/FDD (UMTS Terrestial Radio Access -Frequency Division Duplex) direct-conversion receiver. The direct-conversion receiver is chosen in spite of the well-known problem with DC-offset. The wideband nature of the UMTS signal opens up for simple DC-offset cancellation schemes. In line of this the effect of highpass filtering as a means to reduce the DC-offset is pursued. Based on link-simulations a correlation between DC-offset cancellation and Bit Error Ratio (BER) is established. To PAGE i Jan Hvolgaard Mikkelsen SYSTEM AND CIRCUIT DESIGN ASPECTS FOR CMOS WIRELESS HANDSET RECEIVERS be used in the receiver planning it is found that a third to fourth order Butterworth filter provides sufficient DC-offset cancellation while degrading E b /N 0 only by 0.2 -0.3dB. When an implementation performance surplus is available it is common practice to simplify receiver planning and employ a full separation of different distortion mechanisms. This approach is not an option when a low-cost silicon technology is the target. For a UTRA/FDD receiver the disturbance scenario is complicated as a consequence of continuos transmission and reception. To manage this a simple voltage domain approach to receiver planning is presented. The method allows all interferring components to be considered simultaneously whereby a more optimum receiver design results in comparison with traditional calculations based on manual distribution of distortion effects. Aiming for CMOS implementation the UTRA/FDD requirements are used to specify requirements for all receiver stages in the direct-conversion receiver. Having requirements for both low noise and especially high linearity the mixer stands out as one of the more challenging blocks and has therefore been selected for CMOS implementation in Part III. A modified Gilbert cell mixer topology forms the basis for the quadrature mixer design. The modification is shown to have a 3dB noise advantage over traditional quadrature mixers. As a drawback the mixer is sensitive towards imbalance in the LO voltage levels and for that matter it is necessary to have an accurate LO feed. For direct-downconversion mixers LO leakage represents a significant source to performance degradation. Due to antennalike characteristics and typically large areas the inductor is especially prone to crosstalk. To minimize the coupling to and from inductors the traditional approach is to surround these by guard-ring structures. While guard-rings improve isolation they also form a trade-off between device area and performance. The relation between guard-ring area and inductor performance is evaluated and it is shown that, depending on the size of the guard-ring, the Q-value reduction may be as high as 16% at 2GHz. In continuation of this, various coupling effects for CMOS onchip co-planar spiral inductors are presented. Simple guard-rings are shown to improve isolation between closely spaced adjacent inductors by approximately 10-15dB. At larger distances the gain of having a guard-ring reduces and is eventually found to be zero at a distance of 1000µm. For modeling purposes an extended lumped element model is proposed and found to fit very well with measurements. RESUMÉ Arbejdet dokumenteret i denne afhandling omhandler aspekter af system og kredsløbsdesign for trådløse modtagere og implementering af disse i Complementary Metal Oxide Semiconductor (CMOS) teknologi. Arbejdet er delt op i tre dele, hvoraf del I omhandler RF egenskaberne for CMOS teknologi, del II omhandler radio-modtagere på arkitekturnivau, og del III omhandler implementation af RF kredsløb og komponenter i CMOS teknologi. Gennem sammenligninger praesenteres et historisk forløb, hvor anvendelsen af CMOS til implementering af trådløse applikation er i fokus. Den intense udvikling CMOS har gennemgået beskrives, og begraensningerne i forhold til analog kredsløbsdesign vurderes. Her viser det sig at, manglen på spoler med tilstraekkelig høj Q-faktor er en af de vaesentligste problemer i forhold til at kunne realisere fuldt integrerede RF kredsløb i CMOS. Del II starter med en gennemgang af forskellige modtager-arkitekturer og en diskussion af deres fundamentale problemer i relation til en integration i CMOS. Ud fra standarderne for Universal Mobile Telephone System (UMTS) udledes kravene til en direct-conversion-modtager til UTRA/FDD (UMTS Terrestial Radio Access -Frequency Division Duplex) systemet. Direct-conversion-modtageren vaelges til trods for det velkendte problem med DC-offset. Den store båndbredde anvendt i UMTS gør det muligt at anvende simple teknikker til reduktion af DC-offset. I forlaengelse af dette undersøges PAGE iii Jan Hvolgaard Mikkelsen SYSTEM AND CIRCUIT DESIGN ASPECTS FOR CMOS WIRELESS HANDSET RECEIVERS det om højpas-filtrering er en farbar vej til reduktion af DC-offsettet. Baseret på linksimulering etableres en sammenhaeng mellem DC-offset-reduktion og bitfejl-sandsynlighed (BER). Til brug i den efterfølgende modtager-designfase afdaekkes, at et tredie-eller fjerdeordens Butterworth filter giver tilstraekkelig reduktion af DC-offsettet samtidig med at E b /N 0 kun reduceres med 0.2 -0.3dB. Forudsat at den anvendte implementeringsteknologi kan levere et performanceoverskud, er det normal praksis at simplificere modtager designet ved at betragte de forskellige forstyrrende mekanismer seperat. Denne praksis er ikke mulig når en low-cost Silicium-implementering er målsaetningen. I UTRA/FDD-systemet foregår signaltransmission og modtagelse samtidigt hvilket øger kompleksiteten af modtager-designopgaven. Til håndtering af dette benyttes en fremgangsmetode, der bygger på spaendingsdomaenebeskrivelser. Metoden gør det muligt at betragte samtlige forstyrrende signaler samtidigt, hvorved et mere optimalt modtagerdesign kan opnås til sammenligning med traditionelle teknikker baseret på en manuel fordeling af de forstyrrende effekter. Med en implementering i CMOS for øje specificeres kravene til alle modtagerblokke i en direct-conversion-modtager ud fra UTRA/FDD-kravene. Med krav om både lav støj og høj linearitet skiller mixeren sig ud som en udfordrende blok, hvorfor denne vaelges til implementering i del III. Her danner en modificeret Gilbert-cell-mixer basis for et quadratur-mixerdesign. Modifikationen vises at have en støjfordel på 3dB i sammenligning med mere traditionelle implementeringer. En ulempe ved den valgte topologi er, at den er følsom overfor ubalance i LO-signalet. For en directconversion-modtager er LO-overhør en vaesentlig kilde til performancereduktion. På grund af dens antennelignende udformning og relativt store størrelse er spolen saerdeles tilbøjelig til skabe overhør. For at minimere overhør til og fra spoler benyttes normalt guard-ringstrukture. Udover at reducere overhør medfører guard-rings også et trade-off mellem komponent-areal og performance. Sammenhaengen mellem guard-ringareal og spole-performance analyseres og det vises, at afhaengig af størrelsen på guard-ringen, kan reduktionen i Q-faktor vaere helt op til 16% ved 2GHz. I forlaengelse af dette gennemgås forskellige kilder til overhør og det vises, at simple guard-rings kan reducere overhør mellem taetplacerede spoler med omkring 10 -15dB. Ved større afstande reduceres effekten af guard-ringen og for en afstand på 1000µm ses ikke laengere nogen effekt. Til anvendelse i simuleringer foreslås en model baseret på passive komponenter, og modellen viser sig at stemme saerdeles godt overens med målinger. PAGE iv PhD Dissertation The work presented in the dissertation is part of a larger research project running within the RF Integrated Systems & Circuits (RISC) Division, also Aalborg University. The overall goal is here to exploit the characteristics of state-of-the-art CMOS processes for RF applications. To accomplish this the RISC Division conducts research on all levels of RF integrated circuit design, i.e. system, circuit, and device level. The basis of the work presented in this dissertation falls within all three research areas, a fact also reflected by the structure of the dissertation. The dissertation is divided into an introductory part and subsequently two parts that each provides an extended summary of the work done within the system level as well as the circuit and device areas. Evaluation of CMOS Front-End Receiver Architectures for GSM Handset Applications The paper presents the first direct evaluation of the potential of RF-CMOS for implementing highly integrated receivers for the Global System for Mobilecommunication (GSM). Also, the paper is the first to report results of RF-CMOS receiver evaluations where the performance of the data receiver is included. The two most promising architectural candidates for implementing highly integrable receivers are identified to be the direct-downconversion receiver (DCR) and the low intermediate frequency (Low-IF) receiver. Both receiver architectures are analyzed and link simulations are conducted based on contemporary CMOS performance. The simulations show that an all CMOS Low-IF receiver solution for GSM is realistic. The DCR is shown to suffer from low-frequency noise problems that lead to de-sensitization causing it to fail to meet specifications. The paper concludes that when using contemporary CMOS performance an all-CMOS Low-IF receiver is potential while the DCR presents problems that still need to be solved. CMOS Technology Adjusts to RF Applications This paper is the first part of a two-part feature that takes a first look at RF CMOS technologies and circuits aiming for IMT-2000. This, the first part, provides an overview of advances in CMOS technologies and their importance in relation to analog circuit design. Normally the minimum feature size of a given technology is used as a technology performance indicator. For digital designs this is an appropriate measure as a number of important parameters is positively affected by the continuous downscaling. Traditional analog RF performance metrics, such as gain, noise and linearity are not necessarily improved in the same way. Instead the paper argues that analog improvements come from other digital improvements than downscaling. For instance, as CPU speeds enter the 1 -2GHz range, design techniques previously considered to be exotic analog techniques are finding way into digital designs. As an example, to reduce interconnect resistivity the use of copper is considered as a replacement of alumina and to ease interconnectivity in extremely dense digital designs several metal layers are needed. Both of these, in principle, digital improvements have direct effect on analog circuit performance as the potential inductor performance is significantly improved. Despite such improvements the paper argues that the major limitation is related to the low-resistivity substrate. An overview of the achievable RF performance for CMOS passive devices is provided to illustrate the limitations in device performance. The paper concludes that all the technological innovations are only useful as long as they maintain the low cost advantage of CMOS. RF CMOS Circuits Target IMT-2000 Applications This paper is the second part of the feature looking at RF CMOS technologies and circuits aiming for IMT-2000. The paper is the first to consider the requirements for the coming 3G systems (IMT-2000) while drawing relations to the achievable RF performance of CMOS. Since IMT-2000 requirements are not yet finalized GSM-like RF requirements are expected. In that sense the step from 2G towards 3G should only be a minor PAGE viii PhD Dissertation
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