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Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA
2020
Transactions on Cryptographic Hardware and Embedded Systems
This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of prior work, the accelerators are fully open-sourced, are designed to be constant-time, and can be parameterized at compile-time to support different parameters without the need for re-writing the
doi:10.13154/tches.v2020.i3.269-306
dblp:journals/tches/WangTJBLS20
fatcat:ztxzwdv3jvenfa7p7mhkxolyye