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Efficient Layout Design and Simulation of CMOS Multiplexer by Using Different Technologies

Farooq Pasha, M Tech-Vlsi, B Kotesh Assistant, Imthiazunnisa Begum
unpublished

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In this paper, a multiplexer has been designed and layout simulated using 90nm in Auto generated and semicustom design mode. The schematic of 4:1 multiplexer has been designed using and its equivalent layout is created using micro wind tools. The Performance has been analyzed and compared in terms of area and power. It can be observed from simulated results in semicustom that 75% reduction in area and 6.6% reduction in power
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Farooq Pasha, M Tech-Vlsi, B Kotesh Assistant, Imthiazunnisa Begum. "Efficient Layout Design and Simulation of CMOS Multiplexer by Using Different Technologies."