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Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
2012
IET Computers & Digital Techniques
Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor
doi:10.1049/iet-cdt.2010.0105
fatcat:42oxxsfupbe4joyddqkd4qhyt4