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Design Analysis of a 12.5 GHz PLL in 130 Nm SiGe BiCMOS Process

Kehan Zhu, Vishal Saxena, Xinyu Wu, Sakkarapani Balagopal
2015 2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)  

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A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3 rd -order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz
more » ... e clock with 4.9 ps rms jitter from a 0.05 to 12.5 GHz signal generator. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.
doi:10.1109/wmed.2015.7093690 fatcat:poql3vukpbcytelbxvisjj5uny
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Kehan Zhu, Vishal Saxena, Xinyu Wu, Sakkarapani Balagopal. "Design Analysis of a 12.5 GHz PLL in 130 Nm SiGe BiCMOS Process." 2015 IEEE Workshop on Microelectronics and Electron Devices (WMED) (2015)