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Usually having level-sensitive latches for their speed, high-performance IC designs need to verify the clock schedules. With process variations, the verification needs to compute the probability of correct clocking. Because of complex statistical correlations and accumulated inaccuracy of statistical operations, traditional iterative approaches have difficulty getting accurate results. Instead, a statistical check of the structural conditions for correct clocking is proposed, where the centraldoi:10.1109/tcad.2005.857395 fatcat:cqmjpbnqfjb7rornqwachnaoqi