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Floating-point division and square root implementation using a Taylor-series expansion algorithm with reduced look-up tables
2008 51st Midwest Symposium on Circuits and Systems
Hardware support for floating-point (FP) arithmetic is an essential feature of modern microprocessor design. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important in many modern applications. In this paper, a fused floating-point multiply/divide/square root unit using the Taylor-series expansion algorithm with reduced lookup tables is presented. The implementation results ofdoi:10.1109/mwscas.2008.4616959 fatcat:t2ykzcr57rc7tkiihhck4l4iry