Floating-point division and square root implementation using a Taylor-series expansion algorithm with reduced look-up tables

Taek-Jun Kwon, Jeff Draper
2008 2008 51st Midwest Symposium on Circuits and Systems  
Hardware support for floating-point (FP) arithmetic is an essential feature of modern microprocessor design. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important in many modern applications. In this paper, a fused floating-point multiply/divide/square root unit using the Taylor-series expansion algorithm with reduced lookup tables is presented. The implementation results of
more » ... he proposed fused unit based on standard cell methodology in IBM 90nm technology exhibits that the incorporation of square root function to an existing multiply/divide unit requires only a modest 20% area increase and the same low latency for divide and square root operation can be achieved (12 cycles). The proposed arithmetic unit also exhibits a reasonably good area-performance balance.
doi:10.1109/mwscas.2008.4616959 fatcat:t2ykzcr57rc7tkiihhck4l4iry