Merging Plasmonics and Silicon Photonics Towards Greener and Faster "Network-on-Chip" Solutions for Data Centers and High-Performance Computing Systems [chapter]

Sotirios Papaioannou, Konstantinos Vyrsokinos, Dimitrios Kalavrouziotis, Giannis Giannoulis, Dimitrios Apostolopoulos, Hercules Avramopoulos, Filimon Zacharatos, Karim Hassan, Jean-Claude Weeber, Laurent Markey, Alain Dereux, Ashwani Kumar (+9 others)
2012 Plasmonics - Principles and Applications  
Nevertheless, data communication and power consumption are still daunting issues in Data Centers and HPCs. According to recent predictions made in [4] , the barrier of 10PFlops computing performance should have been overcome in 2012 by a supercomputer that consumes 5MW of power [5]. In addition, [4] predicted that exascale supercomputing machines would consume 20MW having a power efficiency of 1mW/Gb/s [5]. Nonetheless, power consumption in such environments has been proven to be even higher
more » ... n expected: Today's top-ranked supercomputer, the "K computer", has already reached the 10PFlops performance benchmark but at the expense of excessive consumed power that is more than twice [6] the value that was predicted in 2008. All the above imply that the use of optics at inter-rack communication level is not enough for delivering the necessary performance enhancements. Therefore, the optical technology should now be exploited at shrinked networking environments: The penetration of low-energy photonic solutions at board-toboard, chip-to-chip and eventually intra-chip interconnects would yield remarkable savings in energy consumption [7] . The current mainstream photonic route with high integration and low-cost perspectives relies on the Silicon-on-Insulator (SOI) photonics platform, whose growing maturity is soon expected to release Tb/s-scale data transmission and switching capabilities in datacom and computercom units ensuring low latency, low power consumption and chip-scale integration credentials [8] . Even so, photonic devices cannot reach the compactness of their electronic counterparts: the dimensions of traditional optical structures are limited by the fundamental law of diffraction, preventing the way towards high density integration for interfacing with electronics at the nanoscale. This gap in size between photonic and electronic components is called to be bridged by a promising disruptive technology named plasmonics [9]- [11] . The emerging discipline of plasmonics has started to gain ground as the "beyond photonics" chip-scale platform that can enter the interconnect area [12]-[14], holding a great promise for additional reductions in circuit size and increase in energy efficiency. Plasmonics relies on the excitation of surface plasmon polaritons (SPPs) that are electromagnetic waves coupled to oscillations of free electrons in a metal and propagate along a metal-dielectric interface at near the speed of light. These "hybrid" surface waves have transverse magnetic (TM) polarization in nature and their exhibited electromagnetic field intensity reaches its maximum value at the metal surface whereas it decays exponentially while moving away from the metal-dielectric interface [15] . In this way strong intrinsic confinement is feasible even at sub-wavelength scale [16] , breaking the size barriers of diffraction-limited optics and enabling the development of compact integrated nanophotonic circuits [17] . Plasmonic technology does not only succeed in providing light manipulation at sub-wavelength dimensions but at the same time allows for the injection of electrical pulses via the metallic layer, offering thereby a seamless energy-efficient platform for merging light beams with electrical control signals towards "active" operations [18]- [25] . Among the various plasmonic waveguide structures proposed so far (i.e. band-gap structures [26], metallic nanowires [27], V-groove waveguides [28]), the low-energy credentials of plasmonics has been mainly highlighted in the case of dielectric-loaded SPP (DLSPP) waveguides, where a dielectric (e.g. polymer) ridge is deposited on top of a smooth metallic film. As a result, strong sub-wavelength (DLSPP) mode confinement is achieved at the metal-dielectric interface. Nonetheless, this performance comes at the expense of
doi:10.5772/51853 fatcat:ecdrbt7rrrdixndehmjxjlog64