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In this paper, a new architecture for accelerating homomorphic function evaluation on FPGA is proposed. A parallel cached NTT algorithm with an overall time complexity O( √ N log √ N ) is presented. The architecture has been implemented on Xilinx Virtex 7 XC7V1140T FPGA. achieving a 60% utilization ratio. The implementation performs 32-bit 2 16 -point NTT algorithm in 23.8µs, achieving speed-up of 2x over the state of the art architectures. The architecture has been evaluated by computing adoi:10.1109/mwscas.2016.7870149 dblp:conf/mwscas/KhairallahG16 fatcat:tbmbcwl7ifamnpl73ferfnuxjy