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Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications
2017
2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
High performance computing (HPC) applications have parallel code sections that must scale to large numbers of cores, which makes them sensitive to serial regions. Current supercomputing systems with heterogeneous or asymmetric CMPs (ACMP) combine few high-performance big cores for serial regions, together with many low-power lean cores for throughput computing. The low requirements of HPC applications in the core front-end lead some designs, such as SMT and GPU cores, to share front-end
doi:10.1109/ispass.2017.7975265
dblp:conf/ispass/MilicRCR17
fatcat:ubmgox4ir5fczaiz4efhg62ctu