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A power optimization method considering glitch reduction by gate sizing

M. Hashimoto, H. Onodera, K. Tamaru

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Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)
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We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally
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... ed experimentally using 12 benchmark circuits with a 0.5 m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimum-sized circuits. ½ ÁÒØÖÓ Ù Ø ÓÒ The dynamic power dissipation, which is the dominant source of power dissipation, is directly related to the number of signal transitions in a circuit. A signal transition can be classified into two categories; a functional transition(steady-state transition) and a spurious transition(glitch). It is well known that glitches occupy a considerable amount in the signal transitions of a circuit. Reference [1] indicates that the glitch power dissipation accounts for 20% to 70%, and Ref. [2] says 7% to 43%. Also glitches are extremely sensitive to signal propagation characteristics(delay)[3]. If we properly optimize timing characteristics such that the number of glitches is minimized, and if the area(power) cost for the optimization is small, we can expect that the power cost is well overcompensated and overall power dissipation is reduced by the glitch reduction. Gate sizing is an effective method for delay optimization and many solutions are proposed such as Refs. [4, 5, 6] . Gate sizing has been utilized not only for delay optimization but also for power optimization [7, 8, 9, 10] . The main idea of previous approaches for power reduction is to optimize the amount of capacitive load [7, 8] or the amount of capacitive load and short-circuit current[9, 10] based on the transition activity information obtained beforehand. The transition activity, however, is affected by the sizing operation, which is not considered in the optimization. Although Ref. [10] proposes to update the transition information a few times during the optimization, it is not enough to fully consider the sensitivity of glitch activity with respect to timing modification cased by a sizing operation. None of the previous approaches explicitly optimize the number of transitions for power reduction. In this paper, we propose a power optimization method considering glitch reduction by gate sizing. Our method utilizes the sensitivity for reducing power consumed by glitches. Our optimization method consists of two techniques; a statistical estimation method of glitch activities and an optimization algorithm for gate sizing. For the estimation of glitch activities, we classify glitches into two classes; generated glitches and propagating glitches. As for the generated glitches, we adopt a statistical estimation method proposed by Lim and Soma [11] . The propagating glitches, however, are not considered in the method [11] , and therefore we have developed a statistical estimation method. The optimization algorithm needs hill-climbing ability or perturbation process because the power optimization is an ill-behaved problem. A simple greedy algorithm can easily get trapped in a bad local optimal solution. Simulated annealing, however, requires much computational costs. We therefore devise an optimization algorithm which has the ability to escape from a bad local solution while keeping small computational costs. The target of our optimization method is a CMOS combinational circuit designed in a synchronous design style. This paper is organized as follows. Section 2 discusses the glitch estimation method based on a statistical approach. Section 3 explains the optimization algorithm of gate sizing for reducing power dissipation. Section 4 shows some experimental results of our method. Finally Section 5 concludes the discussion. ¾ Ð Ø ×Ø Ñ Ø ÓÒ × ÓÒ ËØ Ø ×Ø Ð ÔÔÖÓ In this section, we explain an estimation method for glitch activities based on a statistical approach. Glitches can be separated into the following two components. generated glitches the glitches which are generated by steadystate (non-glitch) transitions. propagating glitches the glitches which are generated by the glitch transitions propagating from fan-in gates. The first component corresponds to newborn glitches at gate outputs produced by non-glitch transitions of their input signals. Second component corresponds to the glitches produced by glitch transitions of their input signals. Second component, in other words, represents the glitches which are generated previously at a gate in the fan-in direction and propagate through the gate. Hereafter we use the term "generated glitch" to refer to the first component and the term "propagating glitch" to the second component. As for the estimation of generated glitches, a statistical approach is proposed by Lim and Soma [11] . However, the effect of propagating glitches are not taken into account. Some part of the generated glitches may be immediately blocked by the fan-out gates. Other part, however, will propagate through the circuit before they are suppressed. Therefore the effect of the propagating glitches cannot be neglected. In this section, we first briefly explain the statistical method for the estimation of generated glitches [11] . We then propose an estimation method for propagating glitches. With these two methods, we are ready to optimize the circuit for reducing glitches.

doi:10.1109/lpe.1998.708192
fatcat:42bodgalvffdnbthbu7n5tv5ee