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Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
2008
Computer languages, systems & structures
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification.
doi:10.1016/j.cl.2007.06.002
fatcat:quqshvzry5d2zlkaimtu6biatu