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From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems. The large number of scan cells lead to excessive switching activities during the scan shifting operations. In this paper, we present a new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic. This method prevents cumulative transitions caused by shifting operations of thedoi:10.1109/isqed.2015.7085417 dblp:conf/isqed/Seo0LK15 fatcat:2b45mxa7dndl3oembfcsoqhefi