GHz level ultra high speed clock generation and distribution for synchronization becomes a very important technical issue in chip and SoC applications. This paper proposes a novel way of CMOS GHz cellular oscillator/distributor networks with inherent insensitivities to supply-voltage and temperature fluctuations. Simulation results prove that maximun clock skew is limited within ~1% of a system clock period, given 3% of power supply and/or 5% of temperature fluctuations. This technique can thus

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... be used for a low skew clock distribution in a few GHz speed VLSI and SoC systems design. The SPICE simulations are carried out with 3V, 0.5μm CMOS N-well process parameters to prove the novelity as well as the validity of the idea. Layout is also included for the future chip fabrication.