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Memory Access Aware Mapping for Networks-on-Chip
2011
2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications
Networks-on-Chip (NoC) has been introduced to offer high on-chip communication bandwidth for largescale multi-core systems. However, the communication bandwidth between NoC chips and off-chip memories is relatively low, which seriously limits the overall system performance. So optimizing the off-chip memory communication efficiency is a crucial issue in the NoC system design flow. In this paper, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access
doi:10.1109/rtcsa.2011.31
dblp:conf/rtcsa/JinGDY11
fatcat:jtqfhypzifbblowpjwqc6ofpji