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Pipeline architecture for DCT/IDCT
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
In this paper, a unified sequential architecture for 8-point discrete cosine transform and its inverse is described. The architecture is based on rescheduled constant geometry algorithms, which are mapped onto a one-dimensional structure with the aid of vertical projection. The resulting modular architecture can be efficiently pipelined since arithmetic units are removed from the critical path. In addition, the complexity of the architecture is compared to other previously reported architectures operating over sequential data.
doi:10.1109/iscas.2001.922384
dblp:conf/iscas/NikaraTAS01
fatcat:yewpbes3lrbo7kxdoxhtfjdeyu