In this paper, the ways to improve the functionality and reliability of Digital Signal Processors, used to support optical networks, have been studied. Specifically, supported on our finding from previous experimental studies that on-die global interconnects should be described by a distributed RLC model, we propose to model shielded lines, carrying the most critical signals, by a Lossy Transmission Line (LTRA) model. The proposed method obviates the need for tedious simulations, which also due

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... to many inevitably required oversimplifications have a low correlation with a real circuit behavior. The SPICE simulated signal waveforms obtained at the far-end of shielded lines correlate well with experimentally measured waveforms within a typical 45 nm CMOS technology ULSI chip. Based on both, simulations and experimental measurements, we have construed criteria whereby we modified the CMOS driver strength selection guideline to conform to the distributed nature of on-die interconnection lines. The performed simulations on a multi-level clock H-tree structure from a high-performance core block indicate that the new approach considerably improves MOSFETs reliability and power dissipation.