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Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared todoi:10.1109/arith.2011.30 dblp:conf/arith/Nannarelli10 fatcat:4gyv7xxqz5hc7ehvs5ywu43at4