An industrially effective environment for formal hardware verification

C.-J.H. Seger, R.B. Jones, J.W. O'Leary, T. Melham, M.D. Aagaard, C. Barrett, D. Syme
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a generalpurpose functional programming language, which both allows the system to be easily customized and at the same time serves as a
more » ... cification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.
doi:10.1109/tcad.2005.850814 fatcat:rxashd5osrhcjky5mgq2jsodk4