HLTB design for high-speed multi-FPGA pipelines
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
This paper presents the design and implementation of a high-level test bench for high-speed multi-FPGA pipelines, to model and simulate architectures that gather and process large amounts of data. The test bench was successfully employed in a nuclear particle detector system, forming part of a large physics experiment. The design under test consists of three main stages. The first stage simulates the acquisition of the analog input data, providing designers with a means to verify correct
... rify correct operation with unlimited input variation, be it actual or generated data. The second stage, which contains multiple hierarchies of FPGAs, comprises the actual detector firmware design. The last stage is divided into two modules: data acquisition and triggering, which are based on non-synthesizable VHDL features. The simulated system has been verified against the provided technical documentation. Each module was individually tested; subsequently, integration testing of the entire pipeline was carried out to ascertain its physical correctness across design corners. The upfront costs in terms of time and resources required to set up the environment are outweighed by the benefits of having such a system, which range from the scalability, predictability and manageability of modular systems to overcome the associated limitations of high-speed synthesis and instrumentation. Hence, factoring high-level test benches in the design pipeline becomes not just an asset but an invaluable tool for the optimization, testing and verification of complex high-speed designs.