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Low power network on chip architectures: A survey
2020
Computer Science and Information Technologies
Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching
doi:10.11591/csit.v2i3.p158-168
fatcat:rzmirvcyxfao7pu3k2nxsjmhzy