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Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under practical hardware constraints is not known, and even less is understood about the factors that contribute to or limit the performance of control independence. Important aspects of control independence are identified and singled out for study, and a series of idealized machine models are used to isolate and evaluatedoi:10.1109/hpca.1999.744346 dblp:conf/hpca/RotenbergJS99 fatcat:ns45qyk5wzglnayipgcacseine