Implementation of 32 Bit RISC Processor using Reversible Gates

Jyoti Choudhary, Mahesh Kumar Sharma
2019 Zenodo  
Reversible logic is one of the emerging technologies having promising applications in quantum computing. The aim of this project is to design the schematic and simulation for a 32 bit RISC processor using reversible logic peres gate. Beside the functional development, by optimizing the speed of our processor in every block which is inside that, and to minimize the overall delay conventional gates are replaced with reversible gates. This reversible gates which are applicable in Nano technology,
more » ... uantum computing, Low power CMOS, Optical computing. This RISC embodies 15 basic instructions involving Arithmetic, Logical, Data Transfer and control instructions. To implement these instructions the design incorporates various design blocks like Control Unit CU , Arithmetic and Logic Unit ALU , Accumulator, Program Counter PC , Instruction Register IR , Memory and additional logic. Design is implemented and verified in VHDL in Xilinx 14.3. Jyoti Choudhary | Mahesh Kumar Sharma "Implementation of 32-Bit RISC Processor using Reversible Gates" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26709.pdf
doi:10.5281/zenodo.3591488 fatcat:zxz43vurz5fxfarnuysvy2ubjy