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Multi-million gate FPGA physical design challenges
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time due to design automation software runtimes and an increased number of performance based iterations. New FPGA physical design approaches need to be utilized to alleviate some of these problems. Hierarchical approaches to divide and conquer the design, early estimation tools for design exploration, and physical
doi:10.1109/iccad.2003.159780
fatcat:h66lt6ffijhoneb5xx4q6e7hri