A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2014; you can also visit the original URL.
The file type is application/pdf
.
Reliability-aware and energy-efficient synthesis of NoC based MPSoCs
2013
International Symposium on Quality Electronic Design (ISQED)
In sub-65nm CMOS process technologies, networks-onchip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a
doi:10.1109/isqed.2013.6523678
dblp:conf/isqed/ZouP13
fatcat:bgq6c7nynbaolj6lvqm7yu23du