Physical planning with retiming

J. Cong, Sung Kyu Lim
IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)  
In this paper, we propose a uni ed approach to partitioning, oorplanning, and retiming for e ective and e cient performance optimization. The integration enables the partitioner to exploit more realistic geometric delay model provided by the underlying oorplan. Simultaneous consideration of partitioning and retiming under the geometric delay model enables us to hide global interconnect latency e ectively by repositioning FF along long wires. Under the proposedgeometric embedding based p
more » ... ing based p erformance driven partitioning problem, o u r GEO algorithm performs multi-level topdown partitioning while determining the location of the partitions. We adopt the concept of sequential arrival time 14] and develop sequential required time in our retiming based timing analysis engine. GEO performs cluster-move based iterative improvement on top of multi-level cluster hierarchy 4], where the gain function obtained from the timing analysis is based on the minimization of cutsize, wirelength, and sequential slack. In our comparison to (i) state-of-the-art partitioner hMetis 9] followed by retiming 11] and simulated annealing based slicing oorplanning 15], and (ii) state-of-the-art simultaneous partitioning with retiming HPM 7] followed by oorplanning 15], GEO obtains 35% and 23% better delay results while maintaining comparable cutsize, wirelength, and runtime results.
doi:10.1109/iccad.2000.896441 dblp:conf/iccad/CongL00 fatcat:3b4f5atipzht7bp23dg56ltd6u