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An Efficient FFT Engine With Reduced Addressing Logic
2008
IEEE Transactions on Circuits and Systems - II - Express Briefs
In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 -point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a
doi:10.1109/tcsii.2008.2004540
fatcat:imwor2qz7fa7he7ngnwhrj3hd4