Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications [chapter]

Valeriya Kilchytska, Sergej Makovejev, Mohd Khairuddin Md Arshad, Jean-Pierre Raskin, Denis Flandre
2014 Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting  
Ultra-thin body and buried oxide (UTBB) fully depleted (FD) siliconon-insulator (SOI) MOSFETs are widely recognized as a promising candidate for 20 nm technology node and beyond, due to outstanding electrostatic control of short channel effects (SCE). Introduction of a highly-doped layer underneath thin buried oxide (BOX), so called ground-plane (GP), targets suppression of detrimental parasitic substrate coupling and opens multi-threshold voltage (V Th ) and dynamic-V Th opportunities within
more » ... e same process as well as the use of back-gate control schemes [1, 2] . Electrostatics, scalability and variability issues in UTBB MOSFETs as well as their perspectives for low power digital applications are widely discussed in the literature [1] [2] [3] [4] [5] . At the same time assessment of UTBB FD SOI for analog and RF applications received less attention. This chapter will discuss Figures of Merit (FoM) of UTBB MOSFETs of interest for further analog/ RF applications summarizing our original research over the last years [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] . Device analog/RF performance is assessed through the key parameters such as the transconductance, g m , the output conductance, g d , the intrinsic gain, A v and the cutoff frequencies, f T and f max . Particular attention is paid to (1) a wide-frequency band assessment, the only approach that allows fair performance prediction for analog/RF applications; (2) the effect of parasitic elements, whose impact on the device performance increases enormously in deeply downscaled devices, in which they can even dominate device performance. Whenever possible, we will compare FoM achievable in UTBB FD SOI devices with those reported for other advanced devices. 2 Devices UTBB FD SOI MOSFETs discussed in this chapter have been processed at CEA-Leti on UNIBOND TM SOI wafers with either 25 or 10 nm-thick BOX. Wafers without GP, with n-and p-type GP are considered. The Si film in the channel region is thinned down to 7-8 nm, depending on the wafer, and left undoped. Elevated source-drain structures are employed to reduce parasitic resistance. The 28 V. Kilchytska et al.
doi:10.1007/978-3-319-08804-4_2 fatcat:tyfbvqltpjdvdixkl6mu2a4tqi