Reduction of dislocation density in mismatched SiGe/Si using a low-temperature Si buffer layer
Applied Physics Letters
The reduction of the dislocation density in relaxed SiGe/Si heterostructures using a low-temperature Si͑LT-Si͒ buffer has been investigated. We have shown that a 0.1 m LT-Si buffer reduces the threading dislocation density in mismatched Si 0.85 Ge 0.15 /Si epitaxial layers as low as ϳ10 4 cm Ϫ2 . Samples were grown by both gas-source molecular beam epitaxy and ultrahigh vacuum chemical vapor deposition. © 1997 American Institute of Physics. ͓S0003-6951͑97͒03424-4͔ SiGe/Si heterostructures have
... erostructures have gained considerable attention for both electronic and optoelectronic applications due to their compatibility with existing Si technology. 1-5 In particular, there are device applications where a strained Si channel layer of a field-effect transistor needs to be grown on relaxed SiGe to produce a type II heterostructure band lineup. Producing relaxed, nearly defect-free SiGe alloys has been difficult due to the 4% mismatch between Si and Ge. Above the critical thickness, threading dislocations form in the SiGe epilayer, resulting in material degradation and poor device performance. 6 Both superlattices and step-graded layers have been used as techniques to reduce the strain energy while minimizing threading dislocations. 7-13 While some reduction was obtained, 7-9 the dislocation densities are still too high (ϳ10 9 cm Ϫ2 ) for any practical device application. Recent reports indicate that the use of amorphous, polycrystalline, and low-temperature buffer layers can significantly reduce dislocation densities in nitride, InAlAs/InP, and SiGe technologies. 14-16 We have investigated the use of a low-temperature Si ͑LT-Si͒ buffer layer for reducing the threading dislocation density in relaxed SiGe heterostructures. We report the characterization of these heterostructures grown by both gas-source molecular beam epitaxy ͑GSMBE͒ and ultrahigh vacuum chemical vapor deposition ͑UHV-CVD͒, and of heterojunction bipolar transistors ͑HBTs͒ using LT-Si buffers. A number of relaxed SiGe samples with and without the LT-Si buffer layer were grown by GSMBE. Pure Si 2 H 6 and solid Ge were used as source materials. The samples were grown on ͑100͒ p ϩ Si substrates. Each sample consists of a 0.1 m Si layer grown at 700°C followed by a 0.1 m LT-Si buffer layer grown at 450°C. A 0.5 m Si 0.85 Ge 0.15 layer was then grown at 570°C. Growth of the entire structure was monitored by in situ reflection high-energy electron diffraction measurements. The image displayed a streaked (2ϫ1) pattern during growth of Si at 700°C, which turned spotty during growth of the LT-Si buffer layer. The streaked pattern was restored after a few monolayers of growth of SiGe at 570°C. The control sample consists of a 0.1 m Si layer also grown at 700°C followed by a 0.5 m Si 0.85 Ge 0.15 layer grown at 570°C. Each SiGe sample thickness exceeds the thermodynamically stable critical thickness of 0.4 m. 17 The threading dislocation densities were examined by transmission electron microscopy ͑TEM͒ using a JEOL 2000-FX microscope with an accelerating voltage of 200 kV. Both cross-section TEM and plan-view imaging were performed. Bright-field cross-section ͑200͒ imaging of heterostructures without and with the LT-Si buffer layer are shown in Figs. 1͑a͒ and 1͑b͒, respectively. In the samples without the LT-Si buffer layer, the threading dislocations propagate throughout the alloy layer, as expected. An examination by bright field plan-view ͑022͒ imaging indicates a threading dislocation density of 7.56ϫ10 9 Ϯ2.08 cm Ϫ2 in the sample a͒ Electronic mail: firstname.lastname@example.org FIG. 1. Bright field ͑200͒ cross-section TEM images of 0.5 m thick Si 0.85 Ge 0.15 grown at 570°C on ͑100͒ Si substrates ͑a͒ without any lowtemperature Si͑LT-Si͒ buffer and ͑b͒ with a 0.1 m LT-Si buffer layer grown at 450°C. Both samples have a 0.1 m Si buffer layer grown first on the substrate at 700°C.