Phase interpolation technique based on high-speed SERDES chip CDR

Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
2016 Proceedings of the 2015 5th International Conference on Computer Sciences and Automation Engineering   unpublished
This design combines the advantages of CDR CDR circuit two structures PID and PI-based clock data is based on the structure of semi-digital dual loop recovery system. Using TSMC-0.25μm CMOS process to achieve the PLL design, the operating frequency range of 1.6-2.7GHz, and successfully applied a SERDES chip. Small footprint annular VCO wide frequency adjustment range, and can easily produce the CDR SerDes required multi-phase clock.
doi:10.2991/iccsae-15.2016.32 fatcat:qsodgt5ncvfhletudueljn5lym