On Quantifying Fault Patterns of the Mesh Interconnect Networks

F. Safaeia, M. Fathy, A. Khonsari, M. Ould-Khaoua, H. Shafiei, S. Khosravipour
2007 Advanced Information Networking and Applications  
One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peerto-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of
more » ... fault patterns in a 2-D mesh interconnect network including both convex (|-shape, ||-shape, -shape) and concave (L-shape, Ushape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.
doi:10.1109/aina.2007.98 dblp:conf/aina/SafaeiFKOSK07 fatcat:h5jetwsfobah3kfaxklijklrbi