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Two-level hierarchical register file organization for VLIW processors
2000
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. If more registers than those available in the architecture are required, some actions (such as spill code insertion) have to be applied to reduce this pressure, at the expense of some
doi:10.1145/360128.360143
fatcat:ezkz65alirch5bqhneiiosqmze