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On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
2012
ACM Transactions on Reconfigurable Technology and Systems
High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck
doi:10.1145/2133352.2133354
fatcat:easu2jzndvgnpdnkajntjbuu6e