A two stage CMOS power amplifier is implemented in 0.13µm RF CMOS technology using ADS tool operating at 2.4 GHz with dc supply of 2.5 V. Driver stage as the input stage and power stage as the output stage are the two stages. A cascode topology is used in the driver stage and basic topology is used in the power stage. Output power at 1dB compression point is 20.028 dBm and maximum output power delivered by this circuit is 22.002 dBm. Power added efficiency calculated at 1 dB compression point

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... 44.669 % whereas the maximum power added efficiency comes out to be 70.196 %. The input return and output return losses are -11.132 dB and -12.467 dB respectively. Isolation loss and small signal gain are calculated to be -61.889 dB and 43.745 dB respectively. This circuit shows power gain of 42.728 dB at 1dB compression point. The total dc current flowing through this circuit is 0.0901 A. MOSFET only bias circuits are used to reduce total dc current. This circuit is designed for application in WLAN.