A Novel 2X2 Vedic Multiplier Architecture Based on Reversible Logic

Kiran Kumar, B Nagabhushana, Srividya Kedlaya, M Tech Scholar
International Journal of Electrical Electronics & Computer Science Engineering   unpublished
The complexity of the chip is increasing as the advances in CMOS VLSI technology leads to accumulation of more and more devices on the single chip. Due to this high density of the chip, the power dissipation of the chip also increases demanding better low power CMOS VLSI designs. In this paper we are proposing a novel 2x2 multiplier architecture based on vedic sutra "Urdhva Tiyagbhayam", which enhances the speed of the multiplier, further the design is implemented using reversible logic gates in order to achieve low power dissipations.