Aligned carbon nanotubes for through-wafer interconnects

Ting Xu, Zhihong Wang, Jianmin Miao, Xiaofeng Chen, Cher Ming Tan
2007 Applied Physics Letters  
Through-wafer interconnects by aligned carbon nanotube for three-dimensional stack integrated chip packaging applications have been reported in this letter. Two silicon wafers are bonded together by tetra-ethyl-ortho-silicate. The top wafer ͑100 m thick͒ with patterned through-holes allows carbon nanotubes to grow vertically from the catalyst layer ͑Fe͒ on the bottom wafer. By using thermal chemical vapor deposition technique, the authors have demonstrated the capability of growing aligned
more » ... rowing aligned carbon nanotube bundles with an average length of 140 m and a diameter of 30 m from the through holes. The resistivity of the bundles is measured to be 0.0097 ⍀ cm by using a nanomanipulator. Through-wafer interconnects have been proven to be a promising technology to fabricate the next generation threedimensional ͑3D͒ electronic devices or multichip modules. 1-3 Compared to the conventional interconnect technologies, through-wafer interconnects allow signal access from the back side of the devices. By using this method, devices can be assembled together in two dimensions without the packaging gap, which results in the least parasitic losses, resistance-capacitance delay, flight time, and hence, the fastest possible response. 4 A number of integrated circuit ͑IC͒ devices are interconnected in the vertical axis by through-wafer vials filled with copper or other conductive materials. Ji et al. 5 reported through-wafer interconnects by filling polycrystalline silicon into etched holes. However, the interconnects have relatively high electrical resistance ͑ϳ240 ⍀͒ and low aspect ratio ͑ϳ6͒. Recently, Dixit and Miao 1 reported high aspect ratio ͑ϳ15͒ through-wafer copper interconnect columns, which were fabricated by electroplating and have an electrical resistivity of 2.2 ⍀ cm. However, the electromigration of Cu at high current densities ͑10 6 A/cm 2 ͒ is a critical problem in interconnects for high performance electronic applications. 6 Other challenges include increasing oxidation resistance and preventing the diffusion of copper into silicon substrate. In this regard, carbon nanotube becomes an ideal candidate material for electrical interconnects due to its extraordinary electrical, mechanical, and thermal properties. 7 Wei et al. 8 showed that, at 250°C, the current carrying capacity of multiwalled carbon nanotubes ͑MWCNTs͒ did not degrade even after 334 h with current densities of 10 10 A/cm 2 . The mechanical properties of CNTs are also superior to those of conventional packaging materials used in the current IC industry. Growing MWCNTs inside vias with a diameter of 400 nm ͑ϳ1.25 m depth͒ was reported by Kreupl et al. 9 Li et al. 6 also reported a bottom up CNT growing approach. In his work, MWCNTs ͑ϳ1.5 m long͒ are first grown at prespecified locations, and the free gap between individual CNT is filled with SiO 2 by chemical vapor deposition ͑CVD͒ using TEOS. This is followed by chemical mechanical polishing to remove the excess SiO 2 . Both research groups have shown interesting works, yet the effective lengths of CNTs are quite short, which is a limitation for the 3D throughwafer IC packaging. Zhu et al. 10 demonstrated a reproducible process for the growth of CNT bundles up to 400 m with an aspect ratio of 32. These impressive results proved the possibility of growing long CNTs with high aspect ratio. However, the CNTs synthesized by them were standing freely on the silicon surface and not grown from the through holes; in other words, real through-wafer interconnects by using the high aspect ratio CNT bundles had not been accomplished yet. We provide an alternative and a viable solution for through-wafer interconnects. Two wafers are bonded together, and CNT bundles are uniformly grown from the bottom wafer through the holes patterned in the top one. By this method, the length of the CNT can be well controlled by the increasing growth times and different sample orientations. Two silicon ͗100͘ wafers are used and four main steps are included in the fabrication process. In the first step, through holes with diameter ranging from 30 to 60 m are created by deep reactive iron etching 11 ͑DRIE͒ in the top wafer ͑100 m thick͒. A thin sol-gel tetra-ethyl-ortho-silicate ͑TEOS͒ film serves as a bonding layer 12 ͑ϳ100 nm thick͒ and it is deposited onto the top wafer after the DRIE. Secondly, an iron catalyst ͑2 nm thick͒ film is deposited onto the bottom wafer ͑350 m thick with 500 nm thick thermal ox-ide͒ by electron beam evaporator. Thirdly, two wafers are bonded together through the use of a bonding machine ͑SUSS SB6͒ at 400°C. Finally, the bonded wafers are cut into small samples ͑5 ϫ 5 cm 2 ͒ and placed in a 4 in. barrel quartz tube to grow CNT via thermal CVD. a͒ Electronic
doi:10.1063/1.2759989 fatcat:56tfmevl2zbz3id56dug7skh7u