EPSL: Executable Protocol Specification Language

Edmund M Clarke, Yuan Lu, Helmut Veith, Dong Wang
2018
The verification of bus protocols, i.e., of communication protocols between hardware devices as in the case of the well-known PCI bus, is a central problem in hardware verification. Although bus protocol design and verification become increasingly important due to the integration of diverse components in IP Core-based designs, even standard bus protocols are usually specified in English which makes specifications often ambiguous, contradictory and certainly non-executable.
doi:10.1184/r1/6605210.v1 fatcat:f7h2oiagzjf3bgli4aphqbmvli