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In a random testing environment, a significant amount of energy is wasted in the LFSR and in the CUT by useless patterns that do not contribute to fault dropping. Another major source of energy drainage is the loss due to random switching activity in the CUT and in the scan path between applications of two successive vectors. In this work, a new built-in self-test (BIST) scheme for scan-based circuits is proposed for reducing such energy consumption. A mapping logic is designed which modifiesdoi:10.1109/icvd.2003.1183191 dblp:conf/vlsid/BhattacharyaSZ03 fatcat:7liothkoq5hsvajda2klrtmtjy