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A self-aligned silicidation technology for surround-gate vertical MOSFETS
2009 Proceedings of the European Solid State Device Research Conference
We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm nchannel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DlBL. This problem is solved using a frame gate architecture in which the pillardoi:10.1109/essderc.2009.5331579 fatcat:esgwn2vh7fezlhyt3xvn27osui