The Physical Design Implementation of a 32-Bit 5-Stage Pipelined MIPS Processor using SCL 180nm Technology

2019 International Journal of Engineering and Advanced Technology  
The proposed work describes the physical design implementation of a 32-bit 5-stage pipelined MIPS processor. The various blocks of this processor include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. Modified architecture is proposed that leads to significant area reduction by exploiting most of the functional units in a single clock cycle. Also, by increasing the instruction
more » ... g the instruction throughput, the overall performance is increased. The simulation of Verilog design for this project is done in Cadence NCLaunch followed by synthesis using Cadence Genus. The RTL to GDSII implementation is carried out in Cadence Innovus using SCL 180nm Technology. Physical verification is performed in Cadence Virtuoso using Calibre tool.
doi:10.35940/ijeat.b3856.129219 fatcat:pdipf2veijbihillmc4s3kdbwe