A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is
This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode "log-domain" oscillator in a classical PLL topology to obtain these features. The PLL has been fabricated in a 0.6-m 12-GHz BiCMOS process, and measured results show a capture range of 15 MHz at a centerdoi:10.1109/82.718589 fatcat:cmuwvocdp5hlxc462azy4iyiia