A 150-MHz translinear phase-locked loop

A. Payne, A. Thanachayanont, C. Papavassilliou
1998 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode "log-domain" oscillator in a classical PLL topology to obtain these features. The PLL has been fabricated in a 0.6-m 12-GHz BiCMOS process, and measured results show a capture range of 15 MHz at a center
more » ... 15 MHz at a center frequency of 150 MHz. The circuit operates from a single 3-V supply and draws 6 mA at 150 MHz. A phase noise of 080 dBc/Hz at 1 kHz offset was obtained with the PLL locked onto an input reference frequency of 151 MHz. The PLL response to a frequency-modulated input has also been examined, and the demodulated output at 100 kHz showed less than 030-dB total harmonic distortion.
doi:10.1109/82.718589 fatcat:cmuwvocdp5hlxc462azy4iyiia